The present invention relates to a multilayer wiring board, which is usable in a probe card and the like, and a method for testing such a multilayer wiring board, and especially to a multilayer wiring board including a wiring path whose electric capacitance is measured to inspect whether the wiring path is good or bad, and a method for testing such a multilayer wiring board.
A technique for measuring the electric capacitance between a signal line and the grounded layer in a multilayer wiring board to detect a break and a short circuit of the signal line is known and disclosed in Japanese Patent Publication No. 53-10863 A (1978), which will be referred to as the first publication.
The first publication discloses a multilayer wiring board, which includes therein a grounded layer consisting of an overall conductor film. The electric capacitance between the grounded layer and a signal line is measured, and then the measured value is compared to a calculated value of the electric capacitance to detect a break and a short circuit of the signal line.
Referring to FIG. 14, there is shown a sectional view showing the conventional method for testing a multilayer wiring board with the use of the technique described above. A multilayer wiring section 11 is formed on a ceramic substrate 10. The multilayer wiring section 11 has five conductor layers, which include wiring patterns 22, 34, 42, 50 and 60 respectively. These wiring patterns are connected to each other via connecting conductors to make up a three-dimensional wiring path. The fourth conductor layer further includes a grounded pattern 52, which is connected to a test pad 78 located on a surface of the multilayer wiring section 11. Since the three-dimensional wiring path extends to the uppermost wiring pattern 60, it is possible to determine whether the wiring path is good or bad by measuring, with a measuring device 28, an electric capacitance between the test pad 78 and the uppermost wiring pattern 60. When the measured value Cm of electric capacitance differs widely from the calculated value, it can be determined that the wiring path may suffer a break or a short circuit. The calculated value Ct of electric capacitance is a total of a calculated value C1 of electric capacitance between the grounded pattern 52 and the wiring pattern 22 of the first conductor layer, a calculated value C2 of electric capacitance between the grounded pattern 52 and the wiring pattern 34 of the second conductor layer, a calculated value C3 of electric capacitance between the grounded pattern 52 and the wiring pattern 42 of the third conductor layer, a calculated value C4 of electric capacitance between the grounded pattern 52 and the wiring pattern 50 of the fourth conductor layer, and a calculated value C5 of electric capacitance between the grounded pattern 52 and the wiring pattern 60 of the fifth conductor layer.
The conventional testing method described above requires that the normal electric capacitance between the signal line and the grounded layer is known. One solution for finding the known normal capacitance is to prepare the acceptable products having normal electric capacitances (i.e., the products that are ascertained to have no break nor short circuit) for a variety of the multilayer wiring boards, but this solution is troublesome and expensive. Alternatively, the normal electric capacitance may be obtained by calculation as mentioned above, but this solution is unsure about the calculation reliability under the influence of the fluctuations in production quality of the multilayer wiring section.